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redball.gif (326 bytes)Support for SystemC

BulletSupport for Verilog 2001

BulletThird party tools integrated with FinSim®(Specman, Debussy Undertow, Vera, VirSim, HDL Score, Comet, Meteor, NelSim, Pivot, DeskPOD, @Designer 2.1, easyCosim)

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Home of the FinSim Verilog/FinSimMath simulator


Fintronic USA Inc. is committed to developing and delivering high performance Verilog and FinSimMath simulators and IP Generators that enable customers to verify efficiently the functional and timing correctness of their most complex electronic system designs.

Fintronic is listed first among suppliers of Verilog Simulators in EDA CAE WALLCHART 2012.

NEW! FinFilterTM, the FIR Filter generator that generates the filter in gate-level Verilog and the associated test bench using mixed Verilog/FinSimMath.

FinSim® supports FinSimMathTM, an extension of Verilog for Mathematical descriptions. This increases the productivity of implementing mathematical algorithms in ASIC or FPGA because:

1) it supports transformation in small steps from math-level to Verilog RTL in one language and one simulation environment, thus simplifying debugging.

2) bit-accurate models and optimization of formats and sizes comes with little effort, due to patented technology (US Patent Nr 7,930,690 B1) that allows the specification and modification of formats and sizes of operands during simulation.

3) exception management is supported by having implicit "overflow" and "underflow" registers associated with variable precision data containers.



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