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Mixed SystemC/Verilog simlation modeling an inout port at the interface between modules written in different languages


This example runs on FinSim version 10_08_31 or higher. It shows how one can model an inout port of a module described in SystemC that is connected to an inout port of a module described in Verilog. In order to run this example one must execute the following commands:

finvc -systemc io1g.cpp io1g.v
finbuild
TOP.sim

The original design consists of io1go.v and io1go.cpp. Since sc_inout ports are not allowed at the interface between languages the files io1go.v and io1go.cpp have been modified into io1g.v and io1g.cpp respectively.

The file io1go.v is listed below:

module top;
   reg hi_in_ver, hi_in_sc;
   wire hi_inout;
     
   initial begin
       $monitor($time,,"\n hi_in_sc=%b\n, hi_in_ver=%b\n, hi_inout=%b\n", hi_in_sc, hi_in_ver, hi_inout);
       #10;
       hi_in_sc = 1'b1; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'bz; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'b0; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'bz; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'bz; hi_in_ver = 1'b1;
       #10; 
       #10 $finish;
   end // initial begin

ver_scalar ver_scalar1(hi_in_ver, hi_inout);
sysc_scalar sysc_scalar1(hi_in_sc, hi_inout);
endmodule

module ver_scalar (lo_in, lo_inout);
input lo_in;
inout lo_inout;
assign lo_inout = lo_in;

always @(lo_inout_in) begin
  $display("At time %d, lo_inout = %b lo_inout = %b", 
	   $time, lo_inout);
end

endmodule

module sysc_scalar (lo_in, lo_inout);
input lo_in;
inout lo_inout;
(* foreign = SystemC *)
endmodule


The file io1go.cpp is listed below:

#include 

class sysc_scalar : public sc_module {
public:
  sc_in lo_in;
  sc_inout lo_inout;
 

  SC_CTOR(sysc_scalar) : lo_in("lo_in"), 
                         lo_inout("lo_inout")
                        
    {
    SC_METHOD(run);
    sensitive << lo_in << lo_inout;

    SC_METHOD(display);
    sensitive << lo_inout;

  }
    ~sysc_scalar() {}

    void display() {
      cout << "Resolved value is " << lo_inout.read() << " \n";
    }
    void run() {
      lo_inout.write(lo_in.read());
    }   
};
The SystemC file, named here io1g.cpp is listed below:

#include 

class sysc_scalar : public sc_module {
public:
  sc_in lo_in;
  sc_in lo_inout_in;
  sc_out lo_inout_out;

  SC_CTOR(sysc_scalar) : lo_in("lo_in"), 
                         lo_inout_in("lo_inout_in"),
                         lo_inout_out("lo_inout_out")
    {
    SC_METHOD(run);
    sensitive << lo_in;

    SC_METHOD(display);
    sensitive << lo_inout_in;

  }
    ~sysc_scalar() {}

    void display() {
      cout << "Resolved value is " << lo_inout_in.read() << " \n";
    }
    void run() {
      lo_inout_out.write(lo_in.read());
    }   
};

The verilog code is located in the file io1g.v and is listed below:
module top;
   reg hi_in_ver, hi_in_sc;
   wire hi_inout_out_sc, hi_inout_out_ver;
   wire hi_inout;
   
   initial begin
       $monitor($time,,"\n hi_in_sc=%b\n, hi_in_ver=%b\n, hi_inout=%b\n", hi_in_sc, hi_in_ver, hi_inout);
       #10;
       hi_in_sc = 1'b1; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'bz; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'b0; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'bz; hi_in_ver = 1'bz;
       #10; 
       hi_in_sc = 1'bz; hi_in_ver = 1'b1;
       #10; 
       #10 $finish;
   end // initial begin

   assign hi_inout = hi_inout_out_ver;
   assign hi_inout = hi_inout_out_sc;
ver_scalar ver_scalar1(hi_in_ver, hi_inout, hi_inout_out_ver);
sysc_scalar sysc_scalar1(hi_in_sc, hi_inout, hi_inout_out_sc);
endmodule

module ver_scalar (lo_in, lo_inout_in, lo_inout_out);
input lo_in;
input lo_inout_in;
output lo_inout_out;
assign lo_inout_out = lo_in;

always @(lo_inout_in) begin
  $display("At time %d, lo_inout_in = %b lo_inout_out = %b", 
	   $time, lo_inout_in, lo_inout_out);
end

endmodule

module sysc_scalar (lo_in, lo_inout_in, lo_inout_out);
input lo_in;
input lo_inout_in;
output lo_inout_out;
(* foreign = SystemC *)
endmodule


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