Support for FinSimMath
Introduction
FinSimMath's creation was motivated by the need for having mathematical modeling within the Verilog language. This language was designed with the intent that (1) no explicit conversion functions are necessary, (2) runtime changes of formats including the number of bits of the various fields are supported, and (3) data in multi-dimensional arrays are easy to access globally.
FinSimMath suports a large number of mathematical system tasks, and provides access to information regarding the occurrence of overflow, underflow, maximum number of bits needed, and cummulative error.
FinSimMath is an extension of the IEEE std 1364 Verilog language which supports also the types VpDescriptor, VpReg (for variable precision objects), VpComplex, VpPolar, VpFComplex, and VpFPolar types. Logical, Arithmetic and assignment operators are defined to operate on all combination of these types including on arrays and matrixes.
Objects of the variable precison types VpReg, VpComplex, and VpPolar can have their formats (fixed or floating) and the sizes of the format fields modifiable at runtime. This allows for a tight loop in finding optimal formats and sizes of sub-fields, given various costs based on computation accuracy, overflow avoidance, quantization noise, power consumption (switching activity), or other resource constraints.
Global writing to and reading from multi-dimensional arrays are supported using positional system tasks for each range within the system tasks $InitM and $PrintM.
A general form of aliasing using positional system tasks for each dimension of a multi-dimensional array is introduced with the View as construct, enabling to separate data from its location.
A rich mathematical environment is available based on a number of system functions and tasks, including: $VpSin, $VpCos, $VpTan, $VpCtan, $VpAsin, $VpAcos, $VpAtan, $VpActan, VpSinh, $VpCosh, $VpTanh, $VpCtanh, $VpAsinh, $VpAcosh, $VpAtanh, $VpActanh,$VpPow, $VpPow2, $VpLog, $VpLn, $VpAbs, $VpFloor, $VpHypot, $Fft, $Ifft, $Dct, $Idct, etc.
Introduction
- This section describes how rational numeric values are associated to registers declared as variable precision registers (refered heareafter as VP registers), and how those values are manipulated by a set of predefined functions, and overloaded operators in the Verilog language context.
- Super-FinSim supports variable-precision fixed-point and IEEE 754/854 radix 2 floating-point objects, functions, and math operators, using standard Verilog syntax, and custom Verilog semantic extensions1. Beginning with FinSim 10.0 support for the predefined types VpReg and VpDescriptor is also provided as a shorter way to declare VP registers and descriptors. The math operators +, -, *, **, and / can be applied to any combination of the following operands and results formats: arbitrary-precision fixed-point, arbitrary-precision floating-point, Verilog integer, Verilog real, Verilog register, and Verilog supported constants. Trigonometric and hyperbolic (direct and inverse) functions are supported for any precision. Power, logarithm, and square root operations are also available.
Values of VP registers
- The values associated to VP registers are rational values of the form p/q where p is integer and q is an integer power of 2. The general form of the associated value is therefore:
where both p and k are integers.
The value p is allways encoded using some or all the bit values of the VP register.
The encoding scheme for p is present in a descriptor that is associated to the VP register. That descriptor also contains all or part of the information about the value of the exponent k, whose value is in general given the difference between two terms k_fix and k_float. The value of k_fix depends only on information provided in the descriptor, it is not encoded in the bits of the VP register, and can be modified only by changing the descriptor. The value of k_float is encoded using the bits of the VP register and it is often changed during VP register manipulation.
If the descriptor contains all the information about the exponent k (meaning that k_float=0 at all times) the associated values are fixed point values, and the format is a fixed point format. Otherwise, if there is a field in the VP register which encodes k_float using the VP register bit values, the associated values are floating point values, and the format is a floating point format. Under special circumstances, some combination of bit values in the VP register represent special values that are not numeric values. Hereafter, when there is no possible confusion we will refer to the "VP register associated numeric value" as the "numeric value of the VP register". A VP register can also be used as a regular Verilog register and assigned to registers and nets.
The conventions used to declare a VP register, specify the encoding of p, the value of k_fix, the encoding of k_float, the special values and other restrictions are presented in See Specifying VP objects.. The set of available functions and overloaded operations are presented in detail in See VP register manipulation.. Conventions about evaluation of expressions containing VP register elements are presented inSee I/O is not supported in FinSim 8.x for VP registers. However, by using assignments to and from Verilog registers and using Verilog 2001 I/O for Verilog registers, I/O can be performed for VP registers, albeit in an indirect way... See I/O is not supported in FinSim 8.x for VP registers. However, by using assignments to and from Verilog registers and using Verilog 2001 I/O for Verilog registers, I/O can be performed for VP registers, albeit in an indirect way.. contains useful examples uisng the VP register features.
Specifying VP objects
Introduction
There two kinds of VP data containers: registers and wires. VP registers contain values and have associated to them information regarding the format, number of bits used to by the various parts corresponding to the given format (e.g. exponent and mantisa), as well as information regarding rounding and overflow options. VP wires contain values but do not contain any information regarding format, rounding or overflow.
The following four steps are required before using a VP register:
Step 1: Declare a VP descriptor
Step 2: Declare a VP register as data holder
Step 3: Set the descriptor information
Step 4: Associate descriptor to data.
The only order constraints between the steps above are that step 4 should be performed after step 1 and step 2, and step 3 has to be performed after step 1 was performed.
Registers are declared as VP register using the Verilog IEEE std 1364-2001 attribute construct. The attribute varprec is used, having 2 possible values: data and descriptor.
(* varprec = data *) reg [0:511] in1;
(* varprec = descriptor *) reg d1[0:1] d1;
Objects marked with the varprec attribute set to data or declared of type VpReg contain numerical values. The information regarding the format in which the numerical value is represented (i.e. the relation between the numerical value and the bit values of the VP register), as well as the the information regarding the action to be taken in case overflow, or underflow occurs in an operation that assigns to the given VP register is stored in the descriptor that must be associated to any VP register.
VP wires do not have a descriptor associated to them. A VP wire cannot appear in an expression involving more than its name. VP wires are used in order to pass VP values through ports of modules. Wires that are not VP wires are treated as integers when participating in expressions that are assigned to a VP object or that contains a VP object. Therefore, in an assignment to a VP register such as
myWire will be considered an integer, whereas if ti were a VP wire it would be considered to be of the same format and size as myVPreg as in the following example:
It is illegal to have myVPwire declared with a size that is smaller than the necessary number of bits indicated by the descriptor of myVPreg.
i) The size of the register must be chosen such that during the entire simulation it exceeds the number of bits that are necessary to represent the VP register value.
ii) The size of the descriptor register has no particular meaning, however SuperFinsim requires a size of at least two bits.
A descriptor can be associated to any number of VP registers using the system task
$VpAssociateDescriptorToData(myVPreg, myVPregDescriptor);
For each VP register there must be exactly one call associating to it a descriptor. This call must occur in the module in which the VP register is declared.
Setting the fields of the descriptor
The various fields of a descriptor are integers which can be can be modified at runtime any number of times using the system task $VpSetDescriptorInfo(<myVPdescriptor>,<size1>, <size2>, <format>, <roundingOpt>, <overflowOpt>, <miscOpt>).
8.3.2.1 Setting Format and Sizes
The format field can have the following values:
1 - indicates two's complement
4 - indicates floating with no denormals
In case the format is two's complement size1 and size2, if they are both positive, represent the number of bits of the integer part and the number of bits of the fractional part (refered to also as decimal part) respectively. It is illegal for both sizes to be negative. If one is negative the part to which it corresponds (integer or fractional) has zero bits representing it and the other part is represented by a number of bits equal to the sum of the absolute values of the two sizes, with the restriction that no information can be stored in the bits corresponding to the negative size which are located at the border to the other part (i.e. if the integer size is negative the most significative -size1 bits of the fractional part will not be used to store information even if an overflow must be reported. Similarly, in case size2 < 0 the least significative -size2 bits of the integer part will not contain any information even if an underflow must be reported.
In case the format is either floating or floating with no denormals the two sizes must be positive, with size1 representing the number of bits of the sign and the exponent and size2 representing the number of bits of