Finsim Frequently Asked Questions


1. License related questions


1.1 What types of license does Super-FinSim use?

For SunOS, Solaris, HP, and Linux Super-FinSim uses FlexLM from Globetrotter Inc. as the licensing mechanism.
Starting with version 4_5_40 we are using FlexLM 6.1. Previous versions were using FlexLM 4.1. On all platforms that use FlexLM, both floating and nodelocked licenses are available.

For PC-Windows 95/98/NT, Super-FinSim versions prior to 4_7_00 use our proprietary licensing mechanism and only nodelocked licenses are available.
All versions after 4_7_00 use FlexLM 6.1 and both floating and nodelocked licenses are available.

1.2 What types of hostids do Super-FinSim licenses support?

On the platforms on which Super-FinSim uses FlexLM as the licensing mechanism, we support the same hostids as FlexLM. On Linux and Windows, in
addition to the Ethernet address, we support a hardware key based hostid. The hardware key is supplied by Fintronic.

On PC-Windows 95/98/NT we support a hardware key based hostid. The hardware key is supplied by Fintronic.

1.3 Linux specific licensing issues


1.3.1 How do I get the address of my Ethernet card?

On Linux the address of the Ethernet card can be obtained with the command:
/sbin/ifconfig eth0

On Windows NT or 2000 the address of the Ethernet card can be obtained with the command ipconfig/all.
To weed out unnecessary information, you may want to use the following command:
/sbin/ifconfig eth0 | grep eth0 | awk '{print $NF}' | awk -F : '{for (i=1; i<=NF; i++) printf("%s", $i); printf("\n")}'

1.3.2 What do I do with the hardware key?

The hardware key you received from Fintronic goes into one of your serial ports. The hardware key requires a 25-pin serial port. In case
you only have a 9-pin port available, you will need an adapter which can be either purchased directly or requested from Fintronic.

The installation script will attempt to create a symbolic link from /dev/finsim to the port you want to use for the hardware key. For
example if you want to use COM1 for the hardware key, you will need a link from /dev/cua0 to /dev/finsim. The installation script will then
query the hardware key using a program rbuxid which is part of the Super-FinSim distribution.

1.3.3 The installation script hangs while setting up the license. What's wrong?

Most likely, the hardware key is not in the COM port pointed to by /dev/finsim. Make sure that the hardware key is properly plugged in
the correct serial port. To check if you are using the correct port, use the following rules:

If the link is:   then the serial port should be:

/dev/finsim -> /dev/cua0 COM1
/dev/finsim -> /dev/cua1 COM2
/dev/finsim -> /dev/cua2 COM3
/dev/finsim -> /dev/cua3 COM4

Also, please make sure that the serial device has read/write permission for the desired user, for example the following case will allow all users to access the hardware key in COM2:

%ls -l /dev/cua1
crw-rw-rw-   1 root     uucp       5,  65 Feb 11 12:45 /dev/cua1

1.3.4 How do I know if my hardware key works properly?

The Linux Super-FinSim distribution comes with a program called rbuxid, which should be installed in $FINTRONIC/bin/gcc and which
queries the dongle and obtains the dongle id. If the id is returned correctly, the hardware key works properly. If the program hangs or returns a number different from the one written on your hardware key, it does not work properly. A proper functioning example would be:

The hostid of this machine is 0000af5a

where AF5A is the number written on the dongle.

1.4 Windows specific licensing issues.

The downloading results in a file finsim.exe. When executed, it installs the simulator in the directory C:\finsim.  

The directory c:\finsim\bin contains many useful executables. After a normal installation C:\finsim should always be in the
environment variable $path. 

The environment variable LM_LICENSE_FILE must point to the file where the license file (license.dat) received from Fintronic was placed.

To find the value of LM_LICENSE_FILE go to control panel->system->advanced->environment variables

Make sure that the daemons Fintron and Lmgrd are running, by using the -lic_verbose option to finvc.

If they are not running, run c:\finsim\bin\cl\fintron.exe and lmgrd.exe.


1.5 FlexLM licenses issues.


1.5.1 How do I find out if FlexLM is running properly?

You can either check the lmgrd's log file which was specified with the -l option when lmgrd was started, or use one of the utilities provided
together with lmgrd, lmstat and lmdiag.

1.5.2 lmgrd complains about inconsistent encryption codes. What does it mean?

There could be various reasons for this. First, make sure that the license codes in your license $LM_LICENSE_FILE match the ones received from Fintronic. You can change the SERVER name, TCP port number, path to the VENDOR daemon but not much else. Make sure there are no un-escaped <CR> in the middle of a license line.
Second, make sure you are running the correct version of lmgrd. All versions of Super-FinSim after 4_5_40 require lmgrd6.1. Check the
lmgrd's log file for more information.

1.5.3 lmgrd says it cannot start the vendor daemon fintron. What's wrong?

FlexLM 6.1 looks for the vendor daemon in the current directory, the $PATH list, or in the directory where lmgrd is located, if no path is specified on the VENDOR line. If fintron is not in any of the above places, please specify its path on the VENDOR line:

VENDOR fintron /user/admin/license/daemons

Make sure that fintron has execute permission for the user who started lmgrd.

1.5.4 Can I specify a different license file than the one in LM_LICENSE_FILE?

Yes, you can do that with the option -lic <license file>. finvc, finbuild and the simulator all accept this option.

1.5.5 If I have a license for say, Super-FinSim 50K and one for the unlimited version how can I force the simulator to use the 50K one and not the first one available?

Specify the option -lic_type <100K|50K|25K|2K>. finvc, finbuild and the simulator all accept this option.

1.5.6 How do I find out more about FlexLM?

The FlexLM User Manual is available online at and a FAQ for FlexLM is available online at

1.6 The Super-FinSim compiler finvc or the simulator do not run because of license issues. How do I find out what's wrong?

Add the option -lic_verbose to finvc or -verbose to the simulator. This should give you more information about what's going on. Here are a few things to check:

If you are using a FlexLM license, make sure lmgrd is up and running (see 1.5.1). Make sure that the environment variable LM_LICENSE_FILE points to the license file in which you saved the codes received from Fintronic.

If you are using Fintronic's proprietary licensing scheme, please make sure the environment variable FIN_LICENSE_PATH points to the directory in which you have the file fintronc.key in which you saved the codes received from Fintronic.

1.7 How much does it cost to switch my license from one machine to another?

You can switch your license from one machine to another as long as you are under maintenance at no extra cost. You will need to fax or mail a signed statement saying that the old license will not be used any longer.

1.8 If I get a floating license can I run simulations on any platform supported by Super-FinSim?

If you purchase a floating license for any UNIX platform supported by Super-FinSim except Linux, you can use it to run simulations on
any other platforms including Linux. If you purchase a floating license for Linux, you can only run simulations on Linux machines.

2. Displaying waveforms and debugging with Super-FinSim


2.1 What waveform displays and source level debuggers does Super-FinSim support?

Super-FinSim does not provide its own waveform display and source level debugger instead, it is integrated with Debussy from Novas, Undertow from Veritools. Any other waveform/source level debugger that relies on standard PLI as the interface with the simulator will work with Super-FinSim. nWave from Novas which part of the Debussy and Verdi suites is sold as a bundled product with Super-FinSim at a very attractive price. It is also tightly integrated to FinSim with an API interface for better performance

2.2 Does Debussy provide source level debugging?

Yes, it does on Solaris, Linux, and Windows.

2.3 Does Undertow provide source level debugging?

Yes, Undertow supports source level debugging.

2.4 Is there any difference between the Signalscan version offered by Design Acceleration and the one that comes bundled with Super-FinSim?

The OEM Signalscan version that comes bundled with Super-FinSim can only display .trn/.dsn and .sst files generated by Super-FinSim. It
cannot read VCD files.

2.5 Why don't you bundle the latest version of Signalscan on PC-Windows with Super-FinSim?

The latest versions on PC-Windows do not support interactive source level debugging, a feature which many of our customers require. We
will keep bundling the 4.3.5 version until the new versions have support for this feature.

2.6 Does Signalscan run on Linux?

Currently on Linux, Signalscan can only display waveforms from databases generated on other platforms. The Signalscan PLI interface
which generates the .trn/.dsn files does not work on Linux yet. Please contact Design Acceleration for an update on this issue.

2.7 Does Undertow run on Linux?

Yes it does.

2.8 How can I generate debug information for Miscrosoft Developer Studio to be able to debug my PLI on Windows?

You will need to do two things:

  1. invoke finbuild.exe with the +/Zi option
  2. add the following line to finpli.mak:


3. General questions.


3.1 What is the difference between the different simulators you are offering?

Super-FinSim is the top of the line simulator. It comes in 3 other flavors which are different just in the number of components they can
simulate. A component is an instance of a module, a gate, an always or initial block, a continuous assign, etc. The component limitations are
100K, 50K and 25K.

Super-FinSim 2K in addition to a 2K component limitation does not support compiled simulation, PLI and SDF.

FinSim-Developer supports an unlimited number of components but does not support compiled simulation and the ECS (Enhanced Cycle
Simulation) kernel.

3.2 How do I find out how many components my design has?

Specify the option -verbose to the simulator and you should see a line similar to:

Total component count : 103

3.3 Can I upgrade from a lower version of Super-FinSim to a higher one?

Yes, you can upgrade by just paying the difference in the respective list prices.

3.4 I have an evaluation copy of Super-FinSim. How can I find out how FinSim-Developer will run?

For evaluation, we provide the top of the line simulator. In order to get the behavior of FinSim-Developer, just add the options
"+fin_no_ecs" and "-dsm int" to finvc.

3.5 Where do I get the documentation for Super-FinSim?

The documentation for Super-FinSim can be downloaded from our Web site in the Adobe PDF format for which a free reader is available.

3.6 Where do I get the documentation for FinCov?

The User Guide for Super-FinSim contains a chapter dedicated to FinCov.

3.7 How do I use "Save and restart" feature?

Super FinSim can save the state of the simulator and restart thesimulator later on. Both save and restart operations are performed atvery high speed (e.g. 5-6 seconds for saving and 2-3 seconds forrestarting simulation images of 256MB). This feature can be used both to recover after a hardware failure, or to bring the simulation in a certain state, save it and then restart it on many machines simultaneously in order to perform various tests with different stimuli starting from the desired state. This way one does not need to repeat the part where the simulation is brought in the desired state. As an example, one may wish to save the state after the boot cycle is completed and then restart it in order to perform the various tests.

Saving a simulation.

FinSim allows the user to save the state of a simulation in one of two ways. For both cases the user first edits a command file with all the command line options for the simulator and runs the simulation using "-cf <file>"

a. Using the $save("suffix") system task.

The user inserts in the Verilog design at the desired time(s) calls to the system task $save. The simulation is saved in the file(s) finstate..

b. Using the interactive command save

In the interactive mode the user issues the command save . The simulation is saved in the file(s) finstate.. To get to the interactive mode, one can either start the simulation in the interactive mode from the beginning with the "-i" option (specified in the command file), or can insert a $stop in the Verilog source code or can type a CTRL-C while a batch simulation is running.

The following notes apply to saved simulations regardless of how they were saved except where noted.

The simulation state is always saved at the end of the current simulation time. If the design has PLI all misctf routines are invoked with reason 'reason_save'. All of the user's PLI data structures in memory are saved and restored automatically by FinSim however, the user is responsible for saving the state of any file/socket opened using PLI when the misctf routine is called with reason 'reason_save'.

In the interactive mode, if the <suffix> is omitted, the state will be saved in finstate.sav. The system task $save requires a string as its only argument.

Restarting a saved simulation.

To restart a saved simulation, the user has to set the environment variable FIN_RESTART_ARGS to "+fin_restart+ -cf <file>" and call TOP.sim:

# setenv FIN_RESTART_ARGS "+fin_restart+ -cf <file>"

# TOP.sim

<suffix> is the suffix of the saved simulation and <file> containsall command line options for TOP.sim. FinSim allows the user to provide extra plus arguments when the simulation is restarted. This is useful for instance when the design is written such that it generates/applies different test vectors based on one or more plusargs provided at runtime. The user can save the state of the simulation when the initialization sequence is complete and restart the same saved simulation multiple times each with different plus arguments causing the test bench to generate/apply different testvectors for each run. Please note that in order for plus arguments to be evaluated at runtime, the design must be compiled with the option +no_plusargs_substitution to finvc. All plus arguments should be specified in <file>. All other arguments specified when the simulation is restarted will be ignored since the ones in the original run have already been evaluated and are therefore part of the saved image.

If the design has PLI all misctf routines are invoked with reason 'reason_restart'. All of the user's PLI data structures in memory are restored automatically by finsim, however the user is responsible for restoring the state of any file/socket opened using PLI in the initial run when his misctf routine is called with reason 'reason_restart'.

IMPORTANT: Please note that in order to run a new simulation, one has to unsetenv FIN_RESTART_ARGS to avoid restarting a saved one.


3.8 How do I call my own C tasks and functions without using PLI?

Super-FinSim allows the user to call functions written in the C language directly from within the Verilog code. The user only has to provide one or more C header files with the prototypes of the C functions.

The arguments of these C functions can be characters (8 bits), short integers (16 bits) integers (32 bits), long long integers (64
bits) and pointers to them. Super-FinSim assumes that all pointers in the interface correspond to outputs that are going to be written
inside the C functions. All other arguments are assumed to be inputs tothe C functions. The semantics for calling C user functions and tasks are similar to the semantics for calling Verilog or PLI functions andtasks.

The header files providing the prototypes of the C functions are passedto finvc with the -ch <name of header file> option. This option can be specified any number of times if more than one header file is required.  Note that the header files must be self sufficient (as all
well written header files ought to be), i.e. if a header file uses things defined in another header file then the 2nd header file should
be included in the 1st header file. If any of the header files is in a different directory, the user can specify the include directory by
using the +incdir option the same way as for verilog header files.

The object files containing the user C functions can be specified
either in the file finpli.mak in the variable FINUSERCOBJ:

FINUSERCOBJ = example.o

or via the environment variable with the same name:

setenv FINUSERCOBJ example.o

More than one object files can be specified. If used, the file finpli.mak has to be in the local directory where finbuild is called.

If the specified object file does not exist, finbuild will attempt to compile it using a default compilation rule that calls the C compiler
on the corresponding .c file.

3.9 How do I use "Separate Compilation" feature?

1. Super-FinSim provides the facility of separately compiling parts of the Verilog hierarchy. This pre-compiled hierarchy can then be mixed with other Verilog sources to build a new design. This facility is extremely helpful for users who want to ship their IP to their customers but do not want them to access the Verilog source. Not only will the access to the source be denied using the regular `protect/`endprotect mechanism but the IP provider will only have to ship binary files which would make it virtually impossible to re-create the original Verilog code. Another useful application of separate compiled code is for users who add legacy code to their designs which has been tested and will not need to be modified, thus saving compilation time.

This technology for separately compiling Verilog descriptions has been donated by Fintronic USA to the IEEE for standardization within the Verilog 1364 IEEE standard. The standardization that is envisioned based on this donation consists of: (1) option to the compiler to specify which verilog code shall be separately compiled (section 2), (2) option to the compiler to specify which separately compiled code to use in a simulation (section 3), (3) what restrictions shall be placed on a separately compiled code (section 4.1), and (4) what restriction shall be placed on a code that uses the separately compiled code (section 4.2).

This document also contains information regarding the implementation by Fintronic USA, Inc. of the separate compilation of Verilog descriptions

2. Compiling a Verilog Design Hierarchy into object code for later reuse

2.1 A Verilog description can be separately compiled for later reuse by invoking the compiler, called finvc with the special option +sepgen, followed by an invocation of finbuild, as follows:

cmd>finvc +sepgen+


where cmd> is the prompt of the command line, and is a name given by the user to this design. One of the uses of is to make any symbols in the separately compiled design not clash with similar symbols in the final design (which instantiates the separately compiled design). After running these two steps, the temporary directory (fintemp by default) will contain the compiled `C' files, the interpretation data files, the elaboration data files as well as all other files needed for simulating this hierarchy. In addition it will contain a Verilog interface file called interface.v. This file contains the shell for the exported modules in the separately compiled design. Any of these modules can be instantiated in the final design.

2.3 Other options.

finvc also assumes that everything in the separately compiled design except the interface for the top level module is protected. This assumption can be relaxed with the option (+fin_sep_unprotect).

3. Using a separately compiled Verilog design hierarchy

In order to use a separately compiled Verilog design hierarchy as part of a new Verilog design hierarchy one must invoke finvc with the special option +sepuse, followed by finbuild and the invocation of the executable simulator, as follows:

# finvc +sepuse+

# finbuild

# TOP.sim

The directory name is the directory where all the files were generated in the compilation step. More than one such +sepuse options can be specified. In this case finvc treats the file interface.v in the separately compiled directory as a library file, so that any module that is used in the final design and cannot be found is searched in this file.

3. Restrictions on using separately compiled code

3.1. Restrictions on the code instantiating a separately compiled module

A module in the separately compiled code can be instantiated outside of the separately compiled design if and only if:

a) there are no external references anywhere in the the separately compiled design (things like a.b.c).

b) none of its parameters or the parameters of the modules instantiated in the hierarchy below it are overwritten with more than one value.

3.2. Restrictions on the code that is to be separately compiled

A design can instantiate modules from the separately compiled design if and only if:

a) it does not overwrite the parameters of the separately compiled module.

b) it does not make external references into the separately compiled design.

c) its time precision is not finer than the time precision of the separately compiled design.

4. Platform specific questions


4.1 Why are there so many different Linux distributions?

Different Linux distributions (such as RedHat 5.x) come with different versions of the standard C libraries which are not compatible at the library level. This means that if a library is built on one version it will not link properly on a machine using a different version. Therefore the need for multiple distributions.

4.1.1 How do I find out which Linux distribution I have?

The easieast way is to do an:

% ls -l /lib/

Check to which version of libc this link points to and that's the version you want.

4.1.2 I try to run finvc on my Linux machine but it says "Command not found" although the     path is correct and the permissions are properly set. What is  going on?

Most likely you have downloaded the wrong Linux distribution. Please see above.

4.2 Where do I plug in the hardware key?

For Windows, the hardware key goes into the parallel port or if you have a USB key, int the USB port.

For Linux, the hardware key goes into the serial port.

4.2.1 My Linux machine has only a 9-pin serial port available, what do I do?

You need a 9-pin to 25-pin adapter. You can get it from Fintronic USA or any computer store.

4.2.2 Can I chain more than one hardware key or other devices?

Yes you can. Hardware keys from different vendors might cause some conflicts but this has been very rare.

5. Integration with other products questions


5.1 How do I run Super-FinSim and Specman together?

This is a package which for new users of Specman and Finsim. It includes tips on how to integrate the two tools. It also includes an installation test which can be run to make sure you have properly linked Specman with Finsim.
* Directory structure:
This shareware contains the following directories:
e/ - all e sources
sim/ - Files necessary to run simulation installation test

* Tips:

This sample environment can be used to test the Specman/Finsim link.
It consists of one verilog file: xor.v (a simple verilog module with a memory that I want to access) and one e file: shr_finsim_install_top.e (here you can see that we are writing the uint 0 - 9 to each successive memory location and then we print each memory location. We also send in a bunch of xor ops and check the xor operation is correct.
After installing the finsim simulator and setting the proper environmental variables as per the finsim documentation, you can run the example:
To test Finsim with Specman, do the following:
% cd sim
% FIN> $sn
% Specman> @init
% Specman>
% FIN> run ~
(You should see the number 0 - 9 print down the screen.)
% FIN> quit
The test should print out the numbers 0 to 9 for the memory locations that have been written in the verilog from Specman.
When you use finsim with specman on your verilog design, here are a few tips:
Use the scripts "" and "" as templates for your own environment.
In order to have Finsim working with Specman, you need to replace the file "misc.tcl" from your specman installation with the one in this directory. Just do the following:
mv $SPECMAN_HOME/tcl/specman/misc.tcl $SPECMAN_HOME/tcl/specman/misc.tcl.old
cp ./misc.tcl $SPECMAN_HOME/tcl/specman
(Currently this is the misc.tcl from Specman 4.0.2. If you have a different
version of Specman, please contact Fintronic customer support. This will be corrected by Verisity R&D in the near future so this is taken care of automatically.)
Copy the file, finpli.mak, from the finsim installation and the veriuser.c file from the Specman installation:
cp $FIN_INCLUDE_PATH/ finpli.mak
cp $SPECMAN_HOME/src/veriuser.c .
Edit the first line of finpli.make to create the veriuser.o in the current work directory. (See the file finpli.mak in this example.) Edit the veriuser.c file for other pli apps as required.


5.2 How do I run Super-FinSim and Debussy together?

The FinSim family of simulators now support a direct, high performance interface to Debussy so there is no need to link in any PLI. Simply place your $fsdb<...> calls in the Verilog source code and run the simulation as you would normally do. To run FinSim in interactive mode under the Debussy source level debugger, first replace the Debussy resource file debussy.rc your are currently using with this one finsim_debussy.rc.
Add the following options to finvc:
+srcdbg -interactive
and the following options to finbuild:
Run debussy, select FinSim as your simulator and follow Debussy's instructions on how to run a simulation in the interactive mode.

5.3 How do I run Super-FinSim and Undertow together?

To link in Undertow with Super-FinSim, you will need 3 files, You need the files finpli.mak, vt_ptab, iv.v and also the object files vtpli.o and vt_finsimuser.o (from the Undertow distribution kit). The options for finvc should include: -ptab vt_ptab +fullaccess +vtdbg iv.v

How to run Super-Finsim with Undertow in batch mode.

After you built the simulation (using finbuild) and start it (TOP.sim if you didn't specify other name), you can run the Undertow waveform viewer in real-time mode with 'ut -r -v vt.dump' and see the signal changes updated while the simulation is running.

How to run Super-Finsim with Undertow in interactive mode.

After you build the simulation (using finbuild), to run the simulation in interactive mode use 'ut -iv -finsim TOP.sim source_file -sigfile vt.dump', where source_file is one of your Verilog source files included in the simulation. From the Undertow interface, go to Simulation->Run to run the simulation. If you want to see the signal changes in the waveform, after you added the signals to the waveform, press Update, Zoom out or Zoom full buttons.

5.4 How do I run Super-FinSim and SystemC from OSCI together?


i) Currently only version 2.3.1 is supported.

ii) The SystemC library is used in object format with small modifications solely related to public vs private declarations from the version provided by Accellera.

Using Super-FinSim and SystemC together:

i) Use the (* foreign = SystemC *) attribute in the body of the empty Verilog module specification corresponding to each SystemC module used within the Verilog description. Use the exact same characters, since capitalization matters.

Use an interface declarations in SystemC for each Verilog module instantiated within a SystemC module, as in the example shown here.

ii) Run finvc with the option -systemc followed by the name of the .cpp file, for as many files as necessary, e.g. finvc mixed.v -systemc mixed.cpp. Any number of -systemc options can be used in one invocation of finvc.

iii) Run finbuild with all the options available

iv) Run TOP.sim (or the name of the simulator if you specified another name to finbuild), with all the options otherwise available for running the simulator.


i) Run only in batch mode (no interactive support yet).

ii) When instantiating SystemC modules within Verilog or Verilog modules within SystemC make sure that the types of the formal ports match the types of the actual signals connected to the ports.

Use the exact size for the Verilog ports as for the SystemC ports specified in the systemc file. The Verilog ports that are vectors shall be declared in ascending order starting from 0. The corresponding SystemC declarations shall contain the exact size.

iii) Port sizes shall be smaller than 80,000 bits.

iv) SystemC modules that are instantiated in Verilog shall only have ports of types sc_logic and sc_lv, sc_bit, sc_bv corresponding to Verilog counterparts of scalars and vectors of wire and reg. Note that vectors must have more than one bit, otherwise use scalars in the Verilog description of the interface.

v) For running examples, please look at the demo/demo_systemc directory of the Super FinSim distribution and execute finvc -cf or finvc -cf

  Copyright 2002-2016, Fintronic USA, Inc.   All rights reserved.

5.5 How do I use variable precision fixed and floating point computation in Super-FinSim?


i) Please read chapter 8 of Super FinSim 8.0 Users Guide, which can be downloaded in .pdf format from this WEB site (see SUPPORT/FAQ/Download FinSim User's Guide in .pdf format)

ii) Please look at the examples available in finsim/demo/demo_vp of the Super FinSim distribution.


i) Only Super FinSim in compile mode supports variable precision computation.

ii) The commercially available FinSim has a limitation of 127 bits of precision for trigonometric, and hyperbolic functions and of 82 bits for exponential and logarithmic functions. Customized versions may support enhanced precision.

iii) VP registers are limited to 80,000 bits.

  Copyright 2002-2006, Fintronic USA, Inc.   All rights reserved.


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