Our Products
		Super-FinSim Super-FinSim is the top of the line FinSim Verilog simulator. Ever since the first FinSim Verilog simulator has been sold in 1993, the FinSim Verilog simulators have introduced many new features that have become state of the art in Verilog simulation: mixed Compiled and Interpreted simulation, simulation Farm that allows one engineer to manage hundreds of simultaneous simulations, separate and incremental compilation, high performance save and restart, direct integration with C code without the need for PLI, etc. Super FinSim supports the entire Verilog standard IEEE 1364-1995 and many features of IEEE 1364-2001, which are listed under Support for Verilog 2001. It's support includes SDF, VCD, PLI, as well as excellent integration with other tools such as a tight integration via API (for better performance than PLI integration) with Debussy and Verdi debug environments from Novas Software, and excellent PLI integrations with Specman from Verisity and Vera from Synopsys for test benches, MMAV from Denali for memory models, Undertow from Veritools for debug environment, HDLScore from Summit Design for code coverage, and others. In the DA Solution Limited `96 benchmark, the predecessor of Super-FinSim, FinSim-ECS, was rated the fastest Verilog simulator. FinSim was rated the fastest PC-based Verilog simulator in the ASIC & EDA benchmark. Super-FinSim runs on all popular platforms including Sun Solaris 32 and 64 bit, Linux 32 bit from all providers, Linux 64 bit from Madrake or SuSE, Windows NT/2000, Windows 95/98/ME, and XP. FinSim Developer FinSim Developer is an interpreted-only Verilog simulator. It supports the exact same features as Super FinSim with the exception of the not providing compiled simulation and the absence of the ECS kernel for higher performance. In order to make Super FinSim behave exactly like FinSim Developer one must compile the verilog code using +fin_no_ecs -dsm int at the invocation of finvc (the Verilog compiler). FinVA FinVA is a Verilog analyzer of uncommon speed. Its error-checking capabilities are unparalleled, catching errors often ignored by competing products. In addition, it gives a number of warning messages flagging potential design errors such as negative delay expressions, mismatches between types and widths of left and right hand side assignments, accessing array elements out of bounds, etc. The intermediate format generated by the analyzer makes it easy to write back-end applications such as code generators, synthesis programs, design rule checkers, and source code splitters for co-simulation. FinVFI FinVFI is a package of access functions supporting the intermediate format generated by the FinVA analyzer.  It enables users to extract and or modify information in a Verilog design through a procedural interface.  It can be purchased separately as well as part of the FinVA package. FinCov FinCov is a high performance behavioral line coverage tool. Due to its tight integration with the simulation kernel, FinCov has a far smaller overhead and runs much faster than other code coverage tools, which use the PLI interface. It supports merging coverage results from different simulation runs. Site License Site licenses are available. For detailed information contact Alec Stanculescu at alec@fintronic.com. Components and number of lines limitation The component count is number of bi-directional switches + number of gates + number of primitives + number of continuous assignments + number of processes (initial + always) + number of module instantiations in the flattened design. To find out the exact number of components please use the option -verbose when running the simulator: TOP.sim  -verbose (for UNIX) or TOP.EXE -verbose (for Windows). Each limited version also has a limit on the number of lines in the source code. The limit is 3 x number of component limit, for example Super-FinSim 50K has a 50K component limitation and a 150K lines of Verilog source code  limitation. © Copyright 1999-2004, Fintronic USA, Inc.   All rights reserved.